Semiconductor device provided with matrix type current load driving circuits, and driving method thereof

ABSTRACT

A semiconductor device to which active drive current programming is applied, comprising current load cells each having a current load and a current load driving circuit, which are arranged in a matrix, capable of reducing the circuit scale of a current driver with little change made in the structure of the current load driving circuit, and a driving method of the same.  
     A current load cell ( 113, 114 ) includes a current load driving circuit which is provided with a transistor ( 115 ) connected in series with a current load ( 122 ) between first and second power supplies ( 109, 110 ); a capacitance ( 116 ) connected between the control terminal of the transistor ( 115 ) and the first power supply ( 109 ); and switches ( 117, 118 ) connected between the control terminal of the transistor ( 115 ) and a corresponding data line. The output ( 101 ) of a current driver is connected to a plurality of data lines via a selector ( 123, 124 ), and the plural data lines connected to one output of the current driver via the selector and at least one of the switches of each of the current load cells corresponding to the respective data lines are drive-controlled in a time division manner during one horizontal period.

TECHNICAL FIELD

The present invention relates to a semiconductor device provided withcurrent loads and current load driving circuits, and a driving methodthereof, and more particularly, to a semiconductor device in whichcurrent loads and current load driving circuits are arranged in a matrixand an active drive is carried out, and a driving method of the same.

BACKGROUND ART

FIG. 1 is a diagram showing a known structure of a semiconductor devicein which current loads are arranged in a matrix. The semiconductordevice is finding various applications. In FIG. 1, a semiconductordevice 200 comprises a plurality of data lines 202 in a parallelarrangement, a plurality of scanning lines 203 in a parallel arrangementrunning in a direction perpendicular to the data lines 202, and a matrixof current load cells 201 set at the intersections of the data lines 202and scanning lines 203, respectively. The data lines 202 arevoltage-driven or current-driven by a voltage driver or a current driver230. The scanning lines 203 are driven by a scanning circuit 240.Examples of the semiconductor device include an organic EL (ElectroLuminescence) display device in which organic EL elements being currentloads are used as the current load cells 201.

There are two main driving methods for the semiconductor device, inwhich the current loads are arranged in a matrix, as follows:

(1) passive drive by which the lines are selected one by one, and theloads are driven only for a selected period of time; and

(2) active drive by which the lines are selected one by one, the valueof current is memorized by memorizing information for driving the loadsduring a selected period of time, that is, a voltage corresponding tothe value of current fed to each current load, and thereby the loads aredriven with the memorized current value until next time the same line isselected.

A passive driving device is formed of current loads. For example, asshown in FIG. 2 (a), the current load cells 201, which are arranged in amatrix, may be realized from a simple structure with only a plurality ofthe data lines 202, a plurality of the scanning lines 203, and currentloads 206 each being connected between the respective data lines 202 andscanning lines 203. In the passive driving device, however, since theloads are driven only for a selected period of time, a large currentflow is required. Consequently, in the case of the passive drivingdevice, the current loads 206 take heavy loads instantaneously, whichmay cause a problem with the reliability of elements that form thecurrent loads 206. Moreover, the passive driving device consumes ameasurable amount of power because of a drop in efficiency.

On the other hand, in an active driving device, the current load cells201, which are arranged in a matrix, includes a plurality of the datalines 202, a plurality of the scanning lines 203, the current loads 206,and current load driving circuits 207 each of which is connected withthe current load 206 between the data line 202 and the scanning line 203for memorizing a voltage corresponding to the value of current fed toeach current load 206 to drive the load as shown in FIG. 2 (b).

The current load driving circuit 207 in the respective current loadcells 201 is made of a transistor or the like. The current load cell 201has a complex structure as compared to that of the passive drivingdevice. Nevertheless, the active driving device requires a small loaddriving current and the load on the current loads is reduced since theyare driven for a long period of time from when a line is selected towhen next time the same line is selected after all lines are selected.In addition, the active driving device consumes lower amounts of powerbecause of its high efficiency. For the reasons mentioned above, theactive drive may be superior to the passive drive in the load on thecurrent loads and electric power consumption.

The structure of the current load driving circuit 207 for the activedrive is broadly classified into two types: in one type (referred to as“voltage write-in structure”), a voltage to be applied by asemiconductor device (voltage driver 230 in FIG. 1) that feeds therespective current load driving circuits with voltage is memorized, andthe respective loads are driven by a current corresponding to thevoltage memorized; and in another type (referred to as “electric currentprogramming structure”), current is applied by a semiconductor device(voltage driver 230 in FIG. 1) that feeds the respective current loaddriving circuits 207 with current, a voltage corresponding to thecurrent is memorized, and the loads are driven by a currentcorresponding to the current.

Taking an organic EL display device as an example, it is often the casethat current is memorized in an organic EL element of each pictureelement or pixel, and the current load driving circuits are formed ofpolysilicon Thin Film Transistors (abbreviated to “p-Si TFT”).Incidentally, since the p-Si TFT (obtained by low-temperature p-Siprocess) has high field effect mobility, it is possible to integrateparts of peripheral circuits or drivers with the display substrate,which enables high-speed and large-current switching control.

There has been disclosed in Japanese Patent Application laid open No.HEI5-107561 the voltage write-in structure as shown in FIG. 3 (see FIG.7 of the Patent Application). A one-pixel display section 210 comprises:a light emitting element 220 whose one end (anode terminal) is connectedto a power supply line 204; a TFT (Thin Film Transistor) 211 formed ofpolysilicon n-channel MOSFET, whose drain is connected to the other end(cathode terminal) of the light emitting element 220, and whose sourceis connected to a ground line 205; a hold capacitance 212 connectedbetween the gate of the TFT 211 and the ground line 205; and a switch213 placed between the gate of the TFT 211 and a data line 202. Acontrol line K 215 is connected to the control terminal of the switch213, and ON/OFF control is carried out based on a control signal K 215transmitted through the control line K 215 (hereinafter a control lineand a signal transmitted on the control line will be designated by thelike reference numeral). When the control signal K 215 becomes activeand the switch 213 is turned on, the hold capacitance 212 is charged bythe voltage of the data line 202. At the same time, the voltage of thedata line 202 is applied to the TFT 211 as a gate voltage, therebyturning on the TFT 211. Consequently, the current path of the powersupply line 204, the light emitting element 220 and the ground line 205is allowed to conduct, and the light emitting element emits light. Thebrightness or luminance of the light emitting element 220 is changedaccording to the gate voltage of the TFT 211.

However, with the p-Si TFT, there are considerable variations in thecurrent capacity of respective transistors, and therefore, it is highlylikely that the driving current differs between TFTs even when the samevoltage is used. In this case, variations are produced in the brightnessof the organic EL elements, and display accuracy deteriorates.

In order to solve the problem, there has been proposed, for example, inJapanese Patent Application laid open No. HEI1-282419 the electriccurrent programming structure as shown in FIG. 4 (see FIG. 1 of thePatent Application). With this structure, effects are produced only byrelatively small variations in the current capacity of TFTs in adjacentareas, and high-precision display can be achieved.

Referring to FIG. 4, in this circuit, one terminal of the switch 213 inFIG. 3, not the one being connected to the gate of the TFT 211, isconnected to the gate of the TFT 216 (current conversion element) formedof polysilicon n-channel MOSFET, whose gate and drain are connected(i.e. diode-connected) to each other and whose source is connected tothe ground line 205. Besides, the drain of the TFT 216 is connected tothe data line 202 through the switch 214, and the control terminals ofboth the switches 213 and 214 are connected to the control line K 215.The control signal for controlling the brightness of the organic ELelement is fed to the data line as a variable control current. The TFT216 converts the current input into a voltage via the switch 214.

However, a current driver employed for the electric current programmingstructure needs an output circuit for supplying current to respectivedata lines so that it can simultaneously supply current to therespective current load driving circuits on the selected line throughthe data lines during a one-line selection period. Consequently, it isnecessary to provide the current drivers as many as all the data lines,which drives up costs.

In addition, there is another problem in that contact points between thecurrent drivers and a device having current load cells for active drivearranged in a matrix increase, which reduces reliability andproductivity.

Furthermore, it has been considered to form the voltage drivers orcurrent drivers with the p-Si TFT as well as a matrix of organic ELelements and current load driving circuits on the same substrate so asto reduce the number of parts and costs. In this case, however, yields,reliability and productivity decrease because the device as a wholeincreases in circuit size or scale as the circuit scale of currentdriver part becomes larger.

PROBLEMS THAT THE INVENTION IS TO SOLVE

As described above, conventional devices and driving methods haveproblems as follows.

The first problem is that, in a semiconductor device to which activedrive current programming is applied, comprising a matrix of currentloads and current load driving circuits, the cost of current driversincreases, and there is a difficulty in improving productivity andreliability.

This is because there is a need for outputs in the number of data linesof the device comprising a matrix of the current loads and current loaddriving circuits, and therefore, a plurality of current drivers arerequired, which increases the number of parts.

The second problem is that, in a semiconductor device to which activedrive current programming is applied, comprising a matrix of currentloads and current load driving circuits, in the case where thesemiconductor device is provided with built-in current drivers, costsincrease, and there is a difficulty in improving productivity andreliability.

This is because it is necessary to feed all data lines of the devicecomprising a matrix of the current loads and current load drivingcircuits with current supply outputs from the current drivers, andtherefore, the circuit scale of the current drivers becomes larger andthe device as a whole increases in circuit size or scale, which drivesyields down.

It is therefore an object of the present invention to provide asemiconductor device to which active drive current programming isapplied, comprising current load cells each having a current load and acurrent load driving circuit, which are arranged in a matrix, capable ofreducing the circuit scale of a current driver with little change madein the structure of the current load driving circuit, and a drivingmethod of the same.

DISCLOSURE OF THE INVENTION

In accordance with the first aspect of the present invention, to achievethe object mentioned above, there is provided a semiconductor devicethat performs active drive current programming, comprising: current loadcells each having a current load and a current load driving circuit,which are arranged in a matrix; and a means for selecting a plurality ofdata lines one by one with respect to one current output from a currentdriver for supplying current to the respective data lines, and supplyingthe current output to the selected data line; wherein the current loaddriving circuit in each of the current load cells includes a transistorwhose source is connected to a first power supply while whose drain isconnected to the current load directly or via a switch for supplyingcurrent to the current load, a capacitance connected between the gate ofthe transistor and the first power supply or another power supply, and aswitch or a plurality of series-connected switches connected between thegate of the transistor and a corresponding data line; and there arecontrol lines, each of which transmits a signal for controlling theswitch connected to the gate of the transistor included in the currentload driving circuit, at least as many as data lines selectable by onecurrent output of the current driver in one line of the semiconductordevice.

In accordance with another aspect of the present invention, there isprovided a semiconductor device that performs active drive currentprogramming, comprising: current load cells each having a current loadand a current load driving circuit, which are arranged in a matrix; anda means for selecting a plurality of data lines one by one with respectto one current output from a current driver for supplying current to therespective data lines, and supplying the current output to the selecteddata line; wherein the current load driving circuit in each of thecurrent load cells includes a transistor whose source is connected to afirst power supply while whose drain is connected to the current loaddirectly or via a switch for supplying current to the current load, acapacitance connected between the gate of the transistor and the firstpower supply or another power supply, and a plurality of switchesconnected in series between the gate of the transistor and acorresponding data line; there are control lines, each of whichtransmits a signal for controlling the switch whose one end is connectedto the gate of the transistor included in the current load drivingcircuit, at least as many as data lines selectable by one current outputof the current driver in one line of the semiconductor device; and thereare control lines, each of which transmits a signal for controlling theswitch whose one end is connected to the data line corresponding to thecurrent load cell having the current load driving circuit, in each lineof the semiconductor device.

In the semiconductor device according to the present invention, theplural data lines are selected one by one with respect to one currentoutput from the current driver during a one-line selection period (onehorizontal period), and, on the occasion when each data line isselected, current corresponding to that for driving the current load inthe respective current load cells is supplied to the current loaddriving circuit on the selected line and also on the selected data line.

In accordance with yet another aspect of the present invention, there isprovided a method for driving a semiconductor device that performsactive drive current programming and comprises current load cells eachhaving a current load and a current load driving circuit, which arearranged in a matrix, wherein: the output of a current driver forcurrent-driving data lines is input in a selector; the selector selectsthe plural data lines connected respectively to the outputs of theselector one by one based on an output select signal input therein; theoutput of the current driver is supplied to the selected data line; thecurrent load driving circuit in each of the current load cells includesa transistor whose source is connected to a first power supply whilewhose drain is connected to the current load directly or via a switchfor supplying current to the current load, a capacitance connectedbetween the gate of the transistor and the first power supply or anotherpower supply, and a switch or a plurality of series-connected switchesconnected between the gate of the transistor and a corresponding dataline; and there are control lines, each of which transmits a signal forcontrolling the switch in the current load driving circuit, at least asmany as data lines selectable by one current output of the currentdriver in one line of the semiconductor device; comprising: a first stepfor passing current corresponding to the current output supplied fromthe current driver to the selected data line through the transistor inthe current load cell, and setting a voltage that causes the current toflow in the gate of the transistor and the capacitance by turning on theswitch whose one end is connected to the gate of the transistor in thecurrent load cell with a control signal transmitted through one of theplural control lines corresponding to the selected data line during theperiod while the selector selects one of the plural data lines based onthe output select signal in one horizontal period for selecting oneline; and a second step for turning off the switch before or uponcompletion of the select period for the selected data line; wherein thefirst and second steps are performed with respect to each of the pluraldata lines to complete current programming for the current load cellscorresponding to one line.

In accordance with yet another aspect of the present invention, there isprovided a method for driving a semiconductor device that performsactive drive current programming, and comprises: current load cells eachhaving a current load and a current load driving circuit, which arearranged in a matrix; and a means for selecting a plurality of datalines one by one to supply the current output of a current driver forsupplying current to the respective data lines; wherein: the currentload driving circuit in each of the current load cells includes atransistor whose source is connected to a first power supply while whosedrain is connected to the current load directly or via a switch forsupplying current to the current load, a capacitance connected betweenthe gate of the transistor and the first power supply or another powersupply, and a plurality of switches connected in series between the gateof the transistor and a corresponding data line; there are controllines, each of which transmits a signal for controlling the switch whoseone end is connected to the gate of the transistor included in thecurrent load driving circuit, at least as many as data lines selectablefor one output of the current driver in one line of the semiconductordevice; and there are control lines, each of which transmits a signalfor controlling the switch whose one end is connected to the data linecorresponding to the current load cell having the current load drivingcircuit, in each line of the semiconductor device; comprising: a firststep for setting the respective switches whose one ends are connected tothe data lines corresponding to the current load cells for one line tothe on state during one horizontal period with a control signaltransmitted through the control line provided to each line in onehorizontal period for selecting one line; a second step for passingcurrent corresponding to the current output supplied from the currentdriver to the selected data line through the transistor in the currentload cell, and setting a voltage that causes the current to flow in thegate of the transistor and the capacitance by turning on the switchwhose one end is connected to the gate of the transistor in the currentload cell with a control signal transmitted through one of the pluralcontrol lines corresponding to the selected data line during the periodwhile the selector selects one of the plural data lines based on theoutput select signal; and a third step for turning off the switch beforeor upon completion of the select period for the selected data line;wherein the second and third steps are performed with respect to each ofthe plural data lines to complete current programming for the currentload cells corresponding to one line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a semiconductor device in which current loadcells are arranged in a matrix.

FIG. 2 is a diagram showing the configuration of the current load cell:(a) for passive drive, and (b) for active drive.

FIG. 3 is a diagram showing the conventional circuitry of anactive-drive voltage write pixel circuit.

FIG. 4 is a diagram showing the conventional circuitry of anactive-drive current programming pixel circuit.

FIG. 5 is a diagram showing a circuitry according to the firstembodiment of the present invention.

FIG. 6 is a chart showing the timing operation according to the firstembodiment of the present invention.

FIG. 7 is a diagram showing the operating state in a driving period 1according to the first embodiment of the present invention.

FIG. 8 is a diagram showing the operating state in a driving period 2according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a circuitry as a comparative example.

FIG. 10 is a timing chart showing the operation as a comparativeexample.

FIG. 11 is a diagram showing a circuitry according to a modified exampleof the first embodiment of the present invention.

FIG. 12 is a timing chart showing the operation according to themodified example of the first embodiment of the present invention.

FIG. 13 is a diagram showing a circuitry according to the secondembodiment of the present invention.

FIG. 14 is a timing chart showing the operation according to the secondembodiment of the present invention.

FIG. 15 is a diagram showing a circuitry according to a modified exampleof the second embodiment of the present invention.

FIG. 16 is a timing chart showing the operation according to themodified example of the second embodiment of the present invention.

Incidentally, the reference numeral 101 represents current driver oneoutput. The reference numeral 102 represents a first data line (dataline 1). The reference numeral 103 represents a second data line (dataline 2). The reference numeral 104 represents a control line K. Thereference numeral 105 represents a first control line KA. The referencenumeral 106 represents a second control line KB. The reference numeral107 represents a third control line KC. The reference numeral 108represents a fourth control line KD. The reference numeral 109represents a power supply line. The reference numeral 110 represents aground line. The reference numeral 111 represents a first output selectsignal (output select signal 1). The-reference numeral 112 represents asecond output select signal (output select signal 2). The referencenumeral 113 represents a first pixel (pixel 1). The reference numeral114 represents a second pixel (pixel 2). The reference numeral 115represents a first TFT (TFT 1). The reference numeral 116 represents acapacitance. The reference numeral 117 represents a first switch (SW 1).The reference numeral 118 represents a second switch (SW 2). Thereference numeral 119 represents a second TFT (TFT 2). The referencenumeral 120 represents a third switch (SW 3). The reference numeral 121represents a fourth switch (SW 4). The reference numeral 122 representsa light emitting element. The reference numeral 123 represents a firstselector switch (SEL 1). The reference numeral 124 represents a secondselector switch (SEL 2). The reference numeral 200 represents asemiconductor device. The reference numeral 201 represents a currentload cell. The reference numeral 202 represents data line. The referencenumeral 203 represents a scanning line. The reference numeral 204represents a power supply line. The reference numeral 205 represents aground line. The reference numeral 206 represents a current load. Thereference numeral 207 represents a current load driving circuit. Thereference numeral 210 represents a pixel section. The reference numeral211 represents a first TFT (TFT 1). The reference numeral 212 representsa capacitance. The reference numeral 213 represents a first switch (SW1). The reference numeral 214 represents a second switch (SW 2). Thereference numeral 215 represents a control line K. The reference numeral216 represents a second TFT (TFT 2). The reference numeral 220represents a light emitting element. The reference numeral 230represents a voltage driver (current driver). The reference numeral 240represents a scanning circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

A description will be given of embodiments of the present invention. Inaccordance with a preferred embodiment of the present invention, asemiconductor device to which active drive current programming isapplied, comprising current load cells each having a current load and acurrent load driving circuit, which are arranged in a matrix, wherein: aselector (the selector comprised of selector switches 123 and 124 inFIG. 5) selects a plurality of data lines one by one with respect toeach current output (101 in FIG. 5) from a current driver for supplyingcurrent to the respective data lines; the current load driving circuitin each of the current load cells includes a transistor (115 in FIG. 5)whose source is connected to a first power supply (109 in FIG. 5) whilewhose drain is connected to the current load (122 in FIG. 5) directly orvia a switch (switch SW 3 in FIG. 11) for supplying the current load(122) with current corresponding to the current output from the currentdriver fed to the respective data lines via the selector, a capacitance(116) whose one end is connected to the gate of the transistor (115)while the other end is connected to the first power supply (109), and aswitch or a plurality of series-connected switches (117 and 118 in FIG.5) connected between the gate of the transistor (115) and acorresponding data line; and there are control lines (105 and 106),which transmit signals for controlling the switches (117 and 118), atleast as many as data lines which are selectable by the selector (123and 124) for one current output (101) of the current driver in one lineof the semiconductor device. Incidentally, the capacitance (116) may beconnected between the gate of the transistor (115) and another powersupply such as a second power supply (110).

In the semiconductor device according to the present invention, withrespect to one current output (101) of the current driver, the selector(123 and 124) selects the plural data lines one by one during onehorizontal period based on an output select signal input therein. On theoccasion when each data line is selected, current corresponding to thatfor driving the current load in the respective current load cells issupplied to the current load driving circuit of the current load cell onthe selected line and also on the selected data line.

In accordance with the present invention, one output of the currentdriver drives the plural data lines and the current load drivingcircuits corresponding thereto in a time division manner. By virtue ofthis construction, it is possible to reduce the number of necessaryoutputs from the current driver. Consequently, the number of currentdrivers can be reduced, which enables cost reductions as well asenhancement of productivity and reliability. Moreover, since the pluraldata lines are driven by the same output of the current driver, thecurrent of outputs from the current driver varies less as a whole.

Besides, under the method for driving a semiconductor device accordingto an embodiment of the present invention, when an appropriate data lineis selected during one horizontal period, in the current load drivingcircuit on the selected line and also on the selected data line, the oneor plural series-connected switches, whose one end is connected to thegate of the transistor, is/are turned on based on a control signaltransmitted through the corresponding control line. In addition, avoltage corresponding to the current fed through the data line and theswitch is set in the gate of the transistor and one end of thecapacitance, and thereby the transistor memorizes a current value. Afterthat, the one or plural series-connected switches, whose one end isconnected to the gate of the transistor, is/are turned off through thecorresponding control line before or at the completion of selection ofthe data lines.

A different data line is continuously selected, and the current loaddriving circuit on the selected line and also on the selected data linecontrols the one or plural series-connected switches, whose one end isconnected to the gate of the transistor, by a control signal transmittedthrough the different control line than the previous one, whichcorresponds to the selected data line. This operation is repeated, andat the time all the data lines have been selected, one horizontal periodends. The transistor drives the current load according to the currentmemorized therein.

By repeating such one horizontal period for all the lines, the currentload driving circuits drive all the current loads, which are arranged ina matrix, respectively. The repetition of the above operation enablesall the current loads to be always driven by the proper current.

In accordance with the present invention, the semiconductor device maybe provided with control lines, each of which transmits a signal forcontrolling the switch (SW 1 (117)) whose one end is connected to thegate of the transistor (115) in the current load driving circuit of eachcurrent load cell, at least as many as data lines (102 and 103)selectable by the selector (123 and 124) for one current output (101)from the current driver of the semiconductor device; and a control line,which transmits a signal for controlling the switch (SW 2 (118)) andwhose one end is connected to the corresponding data line in the currentload driving circuit, with respect to each line. In other words, aplurality of the current load cells in one line may share the controlline, which transmits a signal for controlling the switch (SW 2 (118))and whose one end is connected to the corresponding data line in each ofthe current load driving circuits.

According to an embodiment of the present invention, in thesemiconductor device to which active drive current programming isapplied, comprising a matrix of the current load cells each having thecurrent load and current load driving circuit, the plural data lines andthe current load driving circuits corresponding thereto can be driven ina time division manner with one output from the built-in current driver.Consequently, it is possible to reduce the number of necessary outputsfrom the current driver. Thereby, the scale or size of a circuit can bereduced, which enables a cost reduction as well as an increase in yield,productivity and reliability. Moreover, since the plural data lines aredriven by the same output of the current driver, the current varies lessaccording to outputs from the current driver on the whole.

Embodiments

Referring now to the drawings, a description of the aforementionedembodiment of the present invention will be given in more detail. In thefollowing, a light emitting display device using light emitting elementsas the current loads will be described. Hereinafter, the current loadcell will be referred to as a pixel, and the current load drivingcircuit will be referred to as a light emitting element driving circuit.However, the light emitting element is cited merely by way of exampleand without limitation. The present invention is applicable for drivingany current load including specific one such as the organic EL element.

FIG. 5 is a diagram showing a circuitry according to the firstembodiment of the present invention. Incidentally, while, in a schematicview of FIG. 5, one of the two data lines 102 and 103 is selected by theselector for one output 101 from the current driver, two or more datalines may be selected in the case, for example, where the driving timecan be reduced. Besides, FIG. 5 shows only two pixel circuits (pixels 1and 2), and data lines 102 and 103 to which the output of the samecurrent driver branches, however, the light emitting display deviceincludes such cells which are arranged in a matrix therein as shown inFIG. 1.

In this embodiment, looking at the first pixel 113 (also referred to as“pixel 1”), the driving circuit for driving the light emitting element122 in the pixel comprises: the first TFT (Thin Film Transistor) 115(also referred to as “TFT 1”) formed of polysilicon p-channel MOSFET,whose source is connected to the power supply 109 and whose drain isconnected to one end of the light emitting element 122, for supplyingcurrent to the light emitting element 122; the capacitance 116 whose oneend is connected to the gate of the first TFT 115 while the other end isconnected to the power supply line 109; the first switch 117 (alsoreferred to as “SW 1”) connected between the gate of the second TFT 119(also referred to as “TFT 2”), whose source is connected to the powersupply line 109 and whose gate and drain are connected (i.e.diode-connected) to each other, and a contact node between the gate ofthe first TFT 115 and the capacitance 116; and the second switch 118(also referred to as “SW 2”) placed between the drain of the second TFT119 and the first data line 102 (also referred to as “data line 1”);wherein the control terminals of both the first and second switches 117and 118 are connected to the control line KA for transmitting thecontrol signal KA.

In the second pixel 114 (also referred to as “pixel 2”), the drain ofthe second TFT 119 is connected to the second data line 103 (alsoreferred to as “data line 2”) through the second switch 118, and thecontrol terminal of the second switch 118 is connected to the controlline KB for transmitting the second control signal KB. The second pixel114 is of essentially the same construction as the first pixel 113except for the connected data line and control line. Incidentally, inthis and the following embodiments, one end of the capacitance 116 ineach pixel is connected to the gate of the first TFT 115, however, theother end may be connected to a power supply other than the power supplyline 109, such as the ground line 110 or other arbitrary power supplies.

The output 101 of the current driver (see current driver 230 in FIG. 1)is connected to the first and second data lines 102 and 103 via thefirst and second switches 123 and 124 (also referred to as “SEL 1 andSEL 2”) which are controlled to be on/off based on the first and secondoutput select signals 111 and 112 (also referred to as “output selectsignal 1 and output select signal 2”) input into their controlterminals, respectively.

As is described above, each of the pixels 113 and 114 is composed of:the TFT 115 for driving the light emitting element 122; the capacitance116; and the series-connected first and second switches (SW 1 and SW 2),which are controlled according to the control signal KA transmittedthrough the first control line KA (105) or the control signal KBtransmitted through the second control line KB (106), and placed betweenthe data line and the gate of the TFT 115 as a drive means; as a basicconstruction (a block indicated by broken lines in FIG. 5). In addition,each of the pixels 113 and 114 further includes: the second TFT 119,whose source is connected to the power supply 109 and whose gate anddrain are shorted to one another, connected between the first and secondswitches 117 and 118 (the first and second TFTs 115 and 119 form acurrent mirror); the power supply line 109; and the ground line 110.Besides, one end of the light emitting element 122 in each pixel isconnected to the drain of the first TFT 115, while the other end isconnected to the ground line 110.

In accordance with this embodiment, differently from the aforementionedJapanese Patent Application laid open No. HEI11-282419, the two pixels113 and 114 are provided with the different control lines KA 105 and KB106, respectively, for controlling the first and second switches 117 and118 in the pixels. Further, the pixels 113 and 114 are provided with theswitches 123 and 124 controlled by the first and second output selectsignals 111 and 112, respectively, for selecting either the first dataline 102 or the second data line 103 to input one output of the currentdriver to each of the two pixels as shown in FIG. 5. Incidentally, whilethe two selector switches 123 and 124 are employed as the selector forallocating the current driver output to the data line 1 or the data line2 based on the output select signals 1 and 2 in this embodiment, theconstruction of the selector is not so limited. As a one-input andmultiple-output selector, any construction may be applicable to theselector. Additionally, in the following description, the switch is onwhen the control signal for the ON/OFF control input into the controlterminal of the switch is at a high level while the switch is in offwhen the control signal is at a low level.

FIG. 6 is a timing chart for explaining the operation according to thefirst embodiment of the present invention. In FIG. 6, the controlsignals KA (105) and KB (106) correspond to the signals transmittedthrough the control lines 105 and 106 of FIG. 5, respectively, and theoutput select signals 1 and 2 correspond to those denoted by referencenumerals 111 and 112 in FIG. 5. During the driving period 1 in theformer part of one horizontal period, the control signal KA (105) isactive while the control signal KB (106) is active during the drivingperiod 2 in the latter part of one horizontal period. Besides, theoutput select signal 1 is active in the former part of one horizontalperiod, and inactive in the latter part. On the other hand, the outputselect signal 2 is inactive in the former part of one horizontal period,and active in the latter part.

One horizontal period is a period for supplying current to pixels in oneline of a matrix of pixels and memorizing the current therein. FIG. 7shows the pixel 1 during the driving period 1 in one horizontal period(see FIG. 6). FIG. 7 is a diagram for explaining the circuit operationof the first pixel 113 in FIG. 5 during the driving period 1 (see FIG.6). Incidentally, it is apparent that respective component parts shownin FIG. 7 correspond to those in FIG. 5.

In the driving period 1 shown in FIG. 6, the control signal KA (105) andthe output select signal 1 are at a H (high) level while the controlsignal KB (106) and the output select signal 2 are at a L (low) level,and the SW 1, SW 2 and SEL 1 of the pixel 1 are on while the SW 1, SW 2and SEL 2 of the pixel 2 are off. Consequently, by the output of thecurrent driver, current Id1 corresponding to the current to be suppliedto the light emitting element of the pixel 1 through the TFT 1 of thepixel 1 is supplied via the data line 1 and SW 1 of the pixel 1 to thesecond thin film transistor TFT 2 of the pixel 1, which operates in thesaturation region because the drain and the gate thereof areshort-circuited.

When the operation of the TFT 2 in the pixel 1 becomes stable, thegate/drain voltage of the TFT 2 in the pixel 1 is such voltage as tocause the flow of current Id1 through the TFT 2 of the pixel 1. Thisvoltage is stored in the capacitance 116 through the SW 2 of the pixel1, and applied to the gate of the TFT 1 in the pixel 1. On thisoccasion, gate-source voltage Vgs1 for the TFT 1 in the pixel 1 isdetermined, and current Idrv1 according to the voltage-currentcharacteristics of the TFT 1 in the pixel 1 is supplied to the lightemitting element 122 of the pixel 1. Thereby, the light emitting element122 of the pixel 1 emits light with brightness determined by thecurrent.

At the end of the driving period 1, the control signal KA (105) is at anL level, and only the SW 1 and SW 2 of the pixel 1 are off. The othercontrol signal remains the same as in the driving period 1. However, theoutput select signal 1 may mark an L level at the same time as thecontrol signal KA (105). In this case, the selector SEL 1 is turned offat the same time as the switch SW 1 of the pixel 1.

During the driving period 2 in one horizontal period, the control signalKA (105) and the output select signal 1 are at an L level while thecontrol signal KB (106) and the output select signal 2 are at an Hlevel, and the SW 1, SW 2 and SEL 1 of the pixel 1 are off, and the SW1, SW 2 and SEL 2 of the pixel 2 are off. Consequently, in the pixel 2during the driving period 1, by the output of the current driver,current Id2 corresponding to the current to be supplied to the lightemitting element 122 of the pixel 2 through the TFT 1 of the pixel 2 issupplied via the data line and SW 1 of the pixel 2 to the TFT 2 of thepixel 2, which operates in the saturation region because the drain andthe gate thereof are short-circuited as in the case of the pixel 1 inthe driving period 1. When the operation of the TFT 2 in the pixel 2becomes stable, the gate/drain voltage of the TFT 2 in the pixel 2 issuch voltage as to cause the flow of current Id2 through the TFT 2 ofthe pixel 2. This voltage is stored in the capacitance 116 through theSW 2 of the pixel 2, and applied to the gate of the TFT 1 in the pixel2. On this occasion, the gate-source voltage of the TFT 1 in the pixel 2is determined, and the current according to the voltage-currentcharacteristics of the TFT 1 in the pixel 2 is supplied to the lightemitting element of the pixel 2. Thereby, the light emitting element ofthe pixel 2 emits light with brightness determined by the current.

FIG. 8 is a diagram for describing the pixel 1 during the driving period2 shown in FIG. 6. In the driving period 2, the SW 1 and SW 2 of thepixel 1 are off. At this time, since the gate and drain of the TFT 2 inthe pixel 1 are short-circuited, a current flows between the drain andthe source until the gate voltage of the TFT 2 becomes almost athreshold voltage of the TFT 2. On the other hand, the gate voltage ofthe TFT 1 in the pixel 1 remains the voltage Vgs1, which has beendetermined in the driving period 1, because the SW 2 of the pixel 1 isoff.

At the end of the driving period 2, as with the driving period 1, thecontrol signal KB (106) is at an L level, and only the SW 1 and SW 2 ofthe pixel 2 have been changed to off. The other control line remains thesame as in the driving period 2. However, the output select signal 2 maymark an L level at the same time as the control signal KB (106). In thiscase, the selector SEL 2 is turned off at the same time as the SW 1 ofthe pixel 2.

The operation described above is performed in one horizontal period.When all the lines undergo such one horizontal period, the driving ofone frame corresponding to one image plane or screen is completed. Thelight emitting display device of the present invention is driven byrepeating the one frame operation.

As is described above, according to this embodiment, the data lines forthe pixels 1 and 2 are selected and driven with one output from thecurrent driver, and the pixels 1 and 2 are controlled by the differentcontrol lines. With this construction, the TFT 2 of the pixel 1 cancontinue to supply the current Idrv1 set in the driving period 1 to thelight emitting element 122 of the pixel 1 without being influenced byvariation in the gate voltage of the TFT 1 in the pixel 1 during thedriving period 2. Thus, the brightness of the light emitting element inthe pixel 1 stays unchanged, and display quality can be maintained.

FIG. 9 is a diagram showing a circuitry presently adopted into a voltagewrite-type active matrix driving device, such as an LCD (Liquid CrystalDisplay), as a comparative example of the present invention. In FIG. 9,the control terminals of the switches SW 1 and SW 2 of the respectivepixels 1 and 2 as shown in FIG. 5 are connected to the same controlline. In this comparative example, the switches 117 and 118 of thepixels 1 and 2 are controlled to be on or off by a control signal 104transmitted through a single control line 104. FIG. 10 is a timing chartshowing the operation. The switches SW 1 and SW 2 of the pixels 1,especially the SW 2, are on during the driving period 2, and therefore,a variation in the gate voltage of the TFT 2 of the pixel 1 during thedriving period 2 is reflected in the gate voltage of the TFT 1 of thepixel 1. Accordingly, the current set in the driving period 1 cannot bepassed through the light emitting element of the pixel 1. For thatreason, the brightness of the light emitting element in the pixel 1varies, and display quality deteriorates.

The basic construction and operation of this embodiment may be appliedto different light emitting element driving circuits than in theaforementioned Japanese Patent Application laid open No. HEI11-282419.For example, a light emitting element driving circuit as shown in FIG.31 of the accompanying drawings of Japanese Patent Application No.2001-259000 (undisclosed when the present application was filed) may beprovided with the basic construction of this embodiment (first TFT 115,capacitance 116, first and second switches 117 and 118), in which thedata line of either the pixel 1 or 2 can be selected with the output ofthe current driver. Referring to FIG. 11, a third switch 120 (SW 3) isplaced between the drain of the first TFT 115 and one end (anodeterminal) of the light emitting element 122, and a fourth switch 121 (SW4) is placed between one end (anode terminal) of the light emittingelement 122 and the ground line 110. The control terminals of the thirdand fourth switches 120 and 121 are connected to a third control line107 (KC) and a fourth control line 108 (KD), respectively.

FIG. 12 is a timing chart showing the operation according to themodified example of the first embodiment illustrated in FIG. 11. Whenthe control signal KC (107) transmitted through the control line KC(107) is at an H level, the switch SW 3 is on, and the light emittingelement 122 is driven by the output current (drain current) from the TFT115 so as to emit light. On the other hand, when the control signal KD(108) transmitted through the control line KC (108) is at an H level,the switch SW 4 is on, and one end of the light emitting element 122 isgrounded. More specifically, referring to FIG. 12, during the drivingperiod 1 in one horizontal period, the output select signal 1 and thecontrol signal KA are at an H level, and the switch SW 1 and SW 2 of thepixel 1 are on. In the meanwhile, the switch SW 3 and SW 4 of the pixel1 are in the off state, and the drain of the TFT 1 and the lightemitting element 122 are not conducting. When the switch SW 1 and SW 2of the pixel 1 are turned on, one end of the capacitance 116 in thepixel 1 is connected to the data line 1 via the switch SW 1 and SW 2 inthe on state, and the terminal voltage of the capacitance 116 (gatevoltage of the TFT 1) is set to a value corresponding to the currentvalue of the current driver output 101. In the following driving period2, the output select signal 2 is at an H level (the output select signal1 is at an L level), the control signal KB is at an H level (the controlsignal KA is at an L level), and the switch SW 1 and SW 2 of the pixel 2are on (the switch SW 1 and SW 2 of the pixel 1 are off). In themeanwhile, the switch SW 3 and SW 4 of the pixel 2 are in the off state,and the drain of the TFT 1 and the light emitting element 122 of thepixel 2 are not conducting. When the switch SW 1 and SW 2 of the pixel 2are turned on, one end of the capacitance 116 in the pixel 2 isconnected to the data line 2 via the switch SW 1 and SW 2 in the onstate, and the terminal voltage of the capacitance 116 (gate voltage ofthe TFT 1) is set to a value corresponding to the current value of thecurrent driver output 101. Subsequently, the output select signal 2 isbrought to be at an L level (the control signals KA and KB are broughtto be at an L level) while the control signal KC common to the pixels 1and 2 is brought to be at an H level. As the switch SW 3 is turned on,the drain of the TFT 1 in the respective pixels 1 and 2 is connected tothe light emitting element 122 via the switch 3 in the on state, and thelight emitting element 122 is fed with the drain current of the TFT 1(the value of the drain current of the TFT 1 depends on the terminalvoltage of the capacitance 116). The light emitting element 122 in eachof the pixels 1 and 2, which has been fed with the drain currentaccording to the gate-source voltage of the TFT 1, emits light withbrightness determined by the current. Thereafter, the control signal KCis brought to be at an L level while the control signal KD is brought tobe at an H level, and one end of the light emitting element 122 isconnected to the ground line 110. Thereby, the light emitting element122 ceases to emit light. The period in which one end of the lightemitting element 122 is connected to the ground line 110 is notrestricted to the example shown in FIG. 12. The connection may beprovided during a desired period set in advance.

According to this embodiment, the scale or size of the pixel isrelatively conventional, however, the number of outputs from the currentdriver is reduced to a half of the number of all the data lines in thelight emitting display device. Accordingly, the number of necessarycurrent drivers is reduced by half. This leads to reductions in costsand the number of parts, and also the contact points between the currentdriver and the light emitting display device are reduced. Thus, it ispossible to improve reliability and productivity.

In the following, the second embodiment of the present invention will bedescribed. Referring to FIG. 13, the first pixel 113 (pixel 1)comprises: the first TFT 115 (TFT 1) formed of polysilicon p-channelMOSFET, whose source is connected to the power supply line 109 and whosedrain is connected to the light emitting element 122, for supplyingcurrent to the light emitting element 122; the capacitance 116 whose oneend is connected to the gate of the first TFT 115 while the other end isconnected to the power supply line 109; the first switch 117 (SW 1)connected between the gate of the second TFT 119 (TFT 2), whose sourceis connected to the power supply line 109 and whose gate and drain areconnected to each other, and a contact node between the first TFT 115and the capacitance 116; and the second switch 118 (SW 2) placed betweenthe drain of the second TFT 119 and the first data line 102 (data line1); wherein the control terminal of the first switch 117 is connected tothe control line KA (105) for transmitting the control signal KA (105)while the second switch 118 is connected to the control line K (104) fortransmitting the control signal K (104).

In the second pixel 114 (pixel 2), the drain of the second TFT 119 isconnected to the second data line 103 (data line 2) through the secondswitch 118, and the control terminal of the first switch 117 isconnected to the control line KB (106) for transmitting the controlsignal KB (106) while the second switch 118 is connected to the controlline K (104) for transmitting the control signal K (104).

In accordance with this embodiment, as can be seen in FIG. 13, the twopixels are provided with the different control lines KA (105) and KB(106), respectively, for controlling the first switch SW 1 in thepixels, and the control line K (104) for controlling the second switchSW 2 in each driving circuit on the same line concurrently. Further, thepixels are provided with the switches 123 and 124 (SEL 1 and SEL 2)controlled by the first and second output select signals 1 and 2,respectively, for selecting either the data line 1 or the data line 2 toinput one output of the current driver to each of the two pixels.

FIG. 14 is a timing chart showing the operation according to thisembodiment. One horizontal period is a period for supplying current topixels in one line of a matrix of pixels and memorizing the currenttherein, during which the aforementioned SW 2 in every light emittingelement driving circuit on the line is on.

In the driving period 1, the control signals K (104) and KA (105) andthe output select signal 1 are at an H level while the control signal KB(106) and the output select signal 2 are at an L level, and the SW 2 ofthe pixel 2 as well as the SW 1, SW 2 and SEL 1 of the pixel 1 are onwhile the SW 1 and SEL 2 of the pixel 2 are off. Consequently, by theoutput of the current driver, current Id1 corresponding to the currentto be supplied to the light emitting element of the pixel 1 through theTFT 1 of the pixel 1 is supplied via the data line and SW 1 of the pixel1 to the TFT 2 of the pixel 1, which operates in the saturation regionbecause the drain and the gate thereof are short-circuited. When theoperation of the TFT 2 in the pixel 1 becomes stable, the gate-drainvoltage of the TFT 2 in the pixel 1 is such voltage as to cause the flowof current Id1 through the TFT 2 of the pixel 1. This voltage is storedin the capacitance through the SW 2 of the pixel 1, and applied to thegate of the TFT 1 in the pixel 1. On this occasion, the gate-sourcevoltage of the TFT 1 in the pixel 1 is determined, and current accordingto the voltage-current characteristics of the TFT 1 in the pixel 1 issupplied to the light emitting element of the pixel 1. Thereby, thelight emitting element 122 of the pixel 1 emits light with brightnessdetermined by the current.

At the end of the driving period 1, the control signal KA (105) is at anL level, and only the SW 1 of the pixel 1 is off. The other controlsignals remain the same as in the driving period 1. However, the outputselect signal 1 may mark an L level at the same time as the controlsignal KA (105). In this case, the SEL 1 is turned off at the same timeas the switch SW 1 of the pixel 1.

During the driving period 2, the control signal KA (105) and the outputselect signal 1 are at an L level while the control signals K (104) andKB (106) and the output select signal 2 are at an H level, and the SW 1and SEL 1 of the pixel 1 are off, and the SW 2 of the pixel 1 as well asthe SW 1, SW 2 and SEL 2 of the pixel 2 are on. Consequently, in thepixel 2 during the driving period 2, by the output of the currentdriver, current Id2 corresponding to the current to be supplied to thelight emitting element 122 of the pixel 2 through the TFT 1 of the pixel2 is supplied via the data line and SW 1 of the pixel 2 to the TFT 2 ofthe pixel 2, which operates in the saturation region because the drainand the gate thereof are short-circuited, as in the case of the pixel 1in the driving period 1. When the operation of the TFT 2 in the pixel 2becomes stable, the gate/drain voltage of the TFT 2 in the pixel 2 issuch voltage as to cause the flow of current Id2 through the TFT 2 ofthe pixel 2. This voltage is stored in the capacitance through the SW 2of the pixel 2, and applied to the gate of the TFT 1 in the pixel 2. Onthis occasion, the gate-source voltage of the TFT 1 in the pixel 2 isdetermined, and current according to the voltage-current characteristicsof the TFT 1 in the pixel 2 is supplied to the light emitting element ofthe pixel 2. Thereby, the light emitting element of the pixel 2 emitslight with brightness determined by the current.

In the driving period 2, the SW 1 of the pixel 1 is off. At this time,since the gate and drain of the TFT 2 in the pixel 1 areshort-circuited, a current flows between the drain and the source untilthe gate voltage of the TFT 2 becomes almost a threshold voltage of theTFT 2 as in the first embodiment. On the other hand, the gate voltage ofthe TFT 1 in the pixel 1 remains the voltage which has been determinedin the driving period 1 because the SW 1 of the pixel 1 is off.

At the end of the driving period 2, as with the driving period 1, thecontrol signal KB (106) is at an L level, and only the SW 1 of the pixel2 has been changed to off. The other control signals remain the same asin the driving period 2.

Thereafter, the output select signal 2 and the control signal K (104)comes to an L level, and the SEL 1, the SW 2 of the pixel 1 and the SW 2of the pixel 2 are turned off. However, the output select signal 2 andthe control signal K (104) may mark an L level at the same time as thecontrol signal KB (106). Whichever of the output select signal 2 or thecontrol signal K (104) may come to an L level previously, they must beat an L level after or at the same time as the control signal KB (106).

The operation described above is performed in one horizontal period.When all the lines undergo such one horizontal period, the driving ofone frame corresponding to one image plane or screen is completed. Thelight emitting display device of the present invention is driven byrepeating the one frame operation.

According to this embodiment, as in the first embodiment describedabove, the data lines for the pixels 1 and 2 are selected and driven byone output from the current driver, and the pixels 1 and 2 arecontrolled by the different control lines. With this construction, theTFT 2 of the pixel 1 can continue to supply the current set in thedriving period 1 to the light emitting element of the pixel 1 withoutbeing influenced by variation in the gate voltage of the TFT 1 in thepixel 1 during the driving period 2. Thus, the brightness of the lightemitting element in the pixel 1 stays unchanged, and display quality canbe maintained.

Besides, according to this embodiment, there is added another controlline common to pixels on one line differently from the first embodiment,and the SW 2 is always on at the end of the driving periods 1 and 2.Consequently, the noise produced when the SW 2 is turned off at the timethe SW 1 of each of the pixels 1 and 2 is turned off causes no effect.Thus, the operation can be more stable as compared to the firstembodiment.

With regard to the basic construction and operation of this embodiment,for example, a light emitting element driving circuit disclosed inJapanese Patent Application No. 2001-259000 (FIG. 31) includes the basicconstruction of this embodiment (encircled by a dotted line), in whichthe data line of either the pixel 1 or 2 can be selected with respect tothe output of the current driver as shown in FIG. 15. Referring to FIG.15, each of the pixels 1 and 2 further comprises, in addition to theconstruction shown in FIG. 13, the third switch 120 (SW 3) placedbetween the drain of the first TFT 115 (TFT 1) and the anode of thelight emitting element 122, and the fourth switch 121 (SW 4) placedbetween the anode of the light emitting element 122 and the ground line110. The control terminals of the third and fourth switches 120 and 121are connected to the third control line KC (107) and the fourth controlline KD (108), respectively. FIG. 16 is a timing chart for explainingthe operation of the device depicted in FIG. 15. When the control signalKC (107) transmitted through the control line KC (107) is at an H level,the switch SW 3 is on, and the light emitting element 122 is driven bythe TFT 115. On the other hand, when the control signal KD (108)transmitted through the control line KC (108) is at an H level, theswitch SW 4 is on, and the anode of the light emitting element 122 isgrounded. ON/OFF control for the switches SW 3 and SW 4 is providedbased on the control signals KC (107) and KD (108) in the same manner asdescribed previously in connection with FIG. 12.

According to this embodiment, as in the first embodiment describedabove, the scale or size of the pixel is relatively conventional,however, the number of outputs from the current driver is reduced to ahalf of the number of all the data lines in the light emitting displaydevice. Accordingly, the number of necessary current drivers is reducedby half. This leads to reductions in costs and the number of parts, andalso the contact points between the current driver and the lightemitting display device are reduced. Thus, it is possible to improvereliability and productivity.

The construction described in the above embodiments may be applicablewith the same operation to the case where the current driver and thelight emitting display device are formed on the same substrate. In thiscase, the number of outputs from the built-in current driver can bereduced by half as compared to the case where the construction of thepresent invention is not adopted, and the circuit scale or size can bereduced. For this reason, it is possible to increase the productionyield as well as reducing costs. Besides, improvements in reliabilityand productivity can be achieved. Incidentally, the TFTs 1 and 2 areformed of pMOS transistors in the above-described embodiments, however,it is obvious that the TFTs may be formed of nMOS transistors. In thiscase, the source of the nMOS transistor TFT 1 (TFT 2) is connected tothe ground line 110, the drain thereof is connected to one end (e.g.cathode terminal) of the light emitting element 122 directly or via theswitch SW 3, and the other end (e.g. anode terminal) of the lightemitting element 122 is connected to the power supply line 109. Whilethe present invention has been described with reference to theparticular illustrative embodiments, it is not to be restricted by theembodiments but only by the appended claims. It is to be appreciatedthat those skilled in the art can change or modify the embodimentswithout departing from the scope and spirit of the present invention.

INDUSTRIAL APPLICABILITY

As set forth hereinabove, in accordance with the present invention,there is provided a semiconductor device which comprises a matrix ofcurrent load cells each having a current load and a current load drivingcircuit, wherein a plurality of data lines are driven by one output of acurrent driver. Consequently, it is possible to reduce the number ofcurrent drivers as well as the number of necessary outputs from thecurrent driver, which enables cost reductions.

Moreover, in accordance with the present invention, since the number ofoutputs from the current driver is reduced, the contact points betweenthe current driver and the device can be reduced. Thus, it is possibleto improve reliability and productivity.

Further, in accordance with the present invention, there is provided asemiconductor device which comprises a built-in current driver and amatrix of current loads and current load driving circuits, wherein aplurality of data lines are driven by one output of the current driver.Therefore, it is possible to reduce the number of necessary outputs fromthe current driver.

Still Further, in accordance with the present invention, since the scaleof the built-in current driver is reduced, the yield increases and thecircuit scale reduces. Thus, cost reductions can be achieved.

1. A semiconductor device that performs active drive currentprogramming, comprising: current load cells each having a current loadand a current load driving circuit, which are arranged in a matrix; anda means for selecting a plurality of data lines one by one with respectto one current output from a current driver for supplying current to therespective data lines, and supplying the current output to the selecteddata line; wherein the current load driving circuit in each of thecurrent load cells includes: a transistor whose source is connected to afirst power supply while whose drain is connected to the current loaddirectly or via a switch; a capacitance connected between the gate ofthe transistor and the first power supply or another power supply; and aswitch or a plurality of series-connected switches connected between thegate of the transistor and a corresponding data line; and wherein thereare control lines for controlling the switch connected to the gate ofthe transistor included in each of the current load driving circuits atleast as many as data lines selectable by one current output of thecurrent driver in one line of the semiconductor device.
 2. Thesemiconductor device claimed in claim 1, further comprising means forperforming operations as follows during one horizontal period forselecting one line: setting a voltage value corresponding to currentfrom one output of the current driver in the gate of the transistor andone end of the capacitance in the current load cell by turning on one ormore switches with a control signal transmitted through one of theplural control lines corresponding to the selected data line so thateach current output of the current driver is electrically connected tothe gate of the transistor in the current load cell during the periodwhile one of the plural data lines is selected; turning off the one ormore switches before or upon completion of the period while one of theplural data lines is selected to maintain the setting voltage; andperforming the above operations with respect to each of the plural datalines to complete current programming for the current load cellscorresponding to one line.
 3. A semiconductor device that performsactive drive current programming, comprising: current load cells eachhaving a current load and a current load driving circuit, which arearranged in a matrix; and a means for selecting a plurality of datalines one by one with respect to one current output from a currentdriver for supplying current to the respective data lines, and supplyingthe current output to the selected data line; wherein the current loaddriving circuit in each of the current load cells includes: a transistorwhose source is connected to a first power supply while whose drain isconnected to the current load directly or via a switch; a capacitanceconnected between the gate of the transistor and the first power supplyor another power supply; and a plurality of switches connected in seriesbetween the gate of the transistor and a corresponding data line; andwherein there are control lines for controlling the switch connected tothe gate of the transistor included in each of the current load drivingcircuits at least as many as data lines selectable by one current outputof the current driver in one line of the semiconductor device; and thereis a control line for controlling the switch whose one end is connectedto the data line corresponding to the current load cell having thecurrent load driving circuit in each line of the semiconductor device.4. The semiconductor device claimed in claim 3, further comprising meansfor performing operations as follows during one horizontal period forselecting one line: setting the respective switches whose one ends areconnected to the data lines corresponding to all the current load cellsfor one line to the on state during one horizontal period with a controlsignal transmitted through the control line provided to each line;setting a voltage value corresponding to current from one current outputof the current driver in the gate of the transistor and one end of thecapacitance in the current load cell by turning on one or more switcheswith a control signal transmitted through one of the plural controllines corresponding to the selected data line so that each currentoutput of the current driver is electrically connected to the gate ofthe transistor in the current load cell during the period while one ofthe plural data lines is selected; turning off the one or more switchesbefore or upon completion of the period while one of the plural datalines is selected to maintain the setting voltage; and performing theabove operations with respect to each of the plural data lines tocomplete current programming for the current load cells corresponding toone line.
 5. A semiconductor device that performs active drive currentprogramming, comprising: current load cells each having a current loadand a current load driving circuit, which are arranged in a matrix; anda means for selecting a plurality of data lines one by one with respectto one current output from a current driver for supplying current to therespective data lines, and supplying the current output to the selecteddata line; wherein the current load driving circuit in each of thecurrent load cells includes: a means for outputting a voltage accordingto the current supplied from the current driver through the data line; ameans for maintaining the voltage; a means for supplying current to thecurrent load according to the voltage maintained; and a means forcontrolling the implementation of the functions according to an inputcontrol signal; and wherein there are control lines for transmitting thecontrol signal at least as many as data lines selectable by one currentoutput of the current driver in one line of the semiconductor device. 6.A semiconductor device that performs active drive current programming,comprising: current load cells each having a current load and a currentload driving circuit, which are arranged in a matrix; and a means forselecting a plurality of data lines one by one with respect to onecurrent output from a current driver for supplying current to therespective data lines, and supplying the current output to the selecteddata line; wherein the current load driving circuit in each of thecurrent load cells includes at least: a means for outputting a voltageaccording to the current supplied from the current driver through thedata line; a means for maintaining the voltage; a means for supplyingcurrent to the current load according to the voltage maintained; a meansfor controlling whether or not to maintain the voltage according to afirst control signal input into the current load cell; and a means forcontrolling whether or not to establish a connection between the dataline and the means for outputting the voltage according to a secondcontrol signal input into the current load cell; and wherein there arecontrol lines for transmitting the first control signal at least as manyas data lines selectable by one current output of the current driver inone line of the semiconductor device; and there is a control line fortransmitting the second control signal in each line of the semiconductordevice.
 7. The semiconductor device claimed in claim 1, wherein thecurrent driver and the semiconductor device are mounted on the samesubstrate.
 8. The semiconductor device claimed in claim 1, wherein thecurrent load is a light emitting element.
 9. The semiconductor deviceclaimed in claim 1, wherein the current load is an organic electroluminescence element.
 10. A semiconductor device driving method fordriving a semiconductor device that performs active drive currentprogramming and comprises current load cells each having a current loadand a current load driving circuit, which are arranged in a matrix,wherein: one current output of a current driver for current-driving datalines is input in a selector, the selector selects the plural data linesconnected respectively to the outputs of the selector one by one basedon an output select signal input therein, and the current output of thecurrent driver is supplied to the selected data line; the current loaddriving circuit in each of the current load cells includes: a transistorwhose source is connected to a first power supply while whose drain isconnected to the current load directly or via a switch for supplyingcurrent to the current load; a capacitance connected between the gate ofthe transistor and the first power supply or another power supply; and aswitch or a plurality of series-connected switches connected between thegate of the transistor and a corresponding data line; and there arecontrol lines for controlling the switch in the current load drivingcircuit at least as many as data lines selectable by one current outputof the current driver in one line of the semiconductor device; thesemiconductor device driving method comprising, in one horizontal periodfor selecting one line: a first step for passing current correspondingto the current output supplied from the current driver to the selecteddata line through the transistor in the current load cell by turning onthe switch whose one end is connected to the gate of the transistor inthe current load cell with a control signal transmitted through one ofthe plural control lines corresponding to the selected data line duringthe period while the selector selects one of the plural data lines basedon the output select signal; and a second step for turning off theswitch before or upon completion of the select period for the selecteddata line; wherein the first and second steps are performed with respectto each of the plural data lines to complete current programming for thecurrent load cells corresponding to one line.
 11. A semiconductor devicedriving method for driving a semiconductor device that performs activedrive current programming and comprises current load cells each having acurrent load and a current load driving circuit, which are arranged in amatrix, wherein: one current output of a current driver forcurrent-driving data lines is input in a selector, the selector selectsthe plural data lines connected respectively to the outputs of theselector one by one based on an output select signal input therein, andthe current output of the current driver is supplied to the selecteddata line, the current load driving circuit in each of the current loadcells includes: a transistor whose source is connected to a first powersupply while whose drain is connected to the current load directly orvia a switch for memorizing and supplying current to the current load; acapacitance connected between the gate of the transistor and the firstpower supply or another power supply; and a plurality of switchesconnected in series between the gate of the transistor and acorresponding data line; there are control lines for controlling theswitch whose one end is connected to the gate of the transistor includedin the current load driving circuit at least as many as data linesselectable by one output of the current driver in one line of thesemiconductor device; and there is a control line for controlling theswitch whose one end is connected to the data line corresponding to thecurrent load cell having the current load driving circuit in each lineof the semiconductor device; the semiconductor device driving methodcomprising, in one horizontal period for selecting one line: a firststep for setting the respective switches whose one ends are connected tothe data lines corresponding to the current load cells for one line tothe on state during one horizontal period with a control signaltransmitted through the control line provided to each line; a secondstep for passing current corresponding to the current output suppliedfrom the current driver to the selected data line through the transistorin the current load cell by turning on the switch whose one end isconnected to the gate of the transistor in the current load cell with acontrol signal transmitted through one of the plural control linescorresponding to the selected data line during the period while theselector selects one of the plural data lines based on the output selectsignal; and a third step for turning off the switch before or uponcompletion of the select period for the selected data line; wherein thesecond and third steps are performed with respect to each of the pluraldata lines to complete current programming for the current load cellscorresponding to one line.
 12. A semiconductor device comprising: aplurality of data lines running in one direction on a substrate; aplurality of control lines running in a direction perpendicular to thedata lines; a plurality of current load cells each of which is set atthe intersection of the respective data lines and control lines, andincludes a current load and a current load driving circuit for drivingthe current load; and a selector having an input terminal to which onecurrent output from a driver for current-driving the data lines isinput, and a plurality of output terminals connected to the plural datalines, respectively; wherein: the selector selects one of the pluraldata lines according to an output select signal input therein, andsupplies the current output from the driver to the selected data line;the plural data lines connected to the selector are connected to theircorresponding current load cells, respectively; the current load drivingcircuit in each of the current load cells includes: a first MOStransistor whose source is connected to a first power supply while whosedrain is connected to one end of the current load directly or via athird switch, the other end of the current load being connected to asecond power supply; a capacitance whose one end is connected to thegate of the first MOS transistor while whose the other end is connectedto the first power supply or another power supply; and a first switchwhose one end is connected to a contact node between the gate of thefirst MOS transistor and one end of the capacitance while whose theother end is connected to a corresponding data line directly or via asecond switch; there are control lines each transmitting a controlsignal corresponding to the first switch or the first and secondswitches of the current load driving circuit in each of the current loadcells connected respectively to the data lines connected to the selectorat least as many as data lines connected to the selector; and in each ofthe plural current load cells, the control signal corresponding to eachof the current load cells is supplied to the control terminal of thefirst switch or the control terminals of both the first and secondswitches of the current load driving circuit.
 13. A semiconductor devicecomprising: a plurality of data lines running in one direction on asubstrate; a plurality of control lines running in a directionperpendicular to the data lines; a plurality of current load cells eachof which is set at the intersection of the respective data lines andcontrol lines, and includes a current load and a current load drivingcircuit for driving the current load; and a selector having an inputterminal to which one current output from a driver for current-drivingthe data lines is input, and a plurality of output terminals connectedto the plural data lines, respectively; wherein: the selector selectsone of the plural data lines according to an output select signal inputtherein, and supplies the current output from the driver to the selecteddata line; the plural data lines connected to the selector are connectedto their corresponding current load cells, respectively; the currentload driving circuit in each of the current load cells includes: a firstMOS transistor whose source is connected to a first power supply whilewhose drain is connected to one end of the current load directly or viaa third switch, the other end of the current load being connected to asecond power supply; a capacitance whose one end is connected to thegate of the first MOS transistor while whose the other end is connectedto the first power supply or another power supply; and a first switchwhose one end is connected to a contact node between the gate of thefirst MOS transistor and one end of the capacitance while whose theother end is connected to a corresponding data line via a second switch;there are at least control lines each transmitting a control signalcorresponding to the first switch of the current load driving circuit ineach of the current load cells connected respectively to the data linesconnected to the selector; there is a control line for transmitting acommon control signal corresponding to the second switch of the currentload driving circuit in each of the current load cells; the controlsignal corresponding to each of the current load cells is supplied tothe control terminal of the first switch of the current load drivingcircuit in the current load cell; and the common control signal issupplied to the control terminal of the second switch of the currentload driving circuit in the current load cell.
 14. The semiconductordevice claimed in claim 12, further comprising a second MOS transistorwhose source is connected to the first power supply and whose gate anddrain are connected to each other; wherein the first switch is connectedbetween the gate of the second MOS transistor and the contact nodeconnecting the gate of the first MOS transistor with one end of thecapacitance; and the second switch is placed between the drain of thesecond MOS transistor and a corresponding data line.
 15. Thesemiconductor device claimed in claim 12, further comprising a fourthswitch between one end of the current load and the second power supply.16. The semiconductor device claimed in claim 12, wherein the first MOStransistor is a TFT.
 17. The semiconductor device claimed in claim 14,wherein the second MOS transistor is a TFT.
 18. The semiconductor deviceclaimed in claim 12, wherein the current load is a light emittingelement.
 19. The semiconductor device claimed in claim 12, wherein thecurrent driver and the semiconductor device are mounted on the samesubstrate.
 20. The semiconductor device claimed in claim 12, wherein thecurrent load is a light emitting element.
 21. The semiconductor deviceclaimed in claim 12, wherein the current load is an organic electroluminescence element.
 22. A semiconductor device driving method fordriving a semiconductor device comprising: a plurality of data linesrunning in one direction on a substrate; a plurality of control linesrunning in a direction perpendicular to the data lines; a plurality ofcurrent load cells each of which is set at the intersection of therespective data lines and control lines, and includes a current load anda current load driving circuit for driving the current load; and aselector having an input terminal to which one current output from adriver for current-driving the data lines is input, and a plurality ofoutput terminals connected to the plural data lines, respectively;wherein: the selector selects one of the plural data lines according toan output select signal input therein, and supplies the current outputfrom the driver to the selected data line; the plural data linesconnected to the selector are connected to their corresponding currentload cells, respectively; the current load driving circuit in each ofthe current load cells includes: a first MOS transistor whose source isconnected to a first power supply while whose drain is connected to oneend of the current load, the other end of the current load beingconnected to a second power supply; a capacitance whose one end isconnected to the gate of the first MOS transistor while whose the otherend is connected to the first power supply or another power supply; anda first switch whose one end is connected to a contact node between thegate of the first MOS transistor and one end of the capacitance whilewhose the other end is connected to a corresponding data line directlyor via a second switch; there are control lines each transmitting acontrol signal corresponding to each of the current load cells connectedrespectively to the data lines connected to the selector; and in each ofthe plural current load cells, the control terminal of the first switchor the control terminals of both the first and second switches of thecurrent load driving circuit are supplied with a control signal throughthe control line set correspondingly to each of the current load cells;the semiconductor device driving method, wherein one cycle is dividedinto a number of driving periods corresponding to the plural currentload cells connected respectively to the plural data lines connected tothe driver via the selector, comprising the steps of: (a) selecting onecorresponding data line from the plural data lines by the selector basedon the output select signal during each driving period corresponding toeach of the plural current load cells; (b) passing current correspondingto the current output supplied from the driver to the data line throughthe first MOS transistor in the current load cell by turning on thefirst switch or the first and second switches in the current load cellwith a control signal transmitted through one of the control lines forthe current load cell corresponding to the data line selected by theselector; and (c) turning off the first switch or the first and secondswitches in the current load cell with a control signal transmittedthrough the control line for the current load cell corresponding to thedata line selected at step (a) before or at the time the selectorproceeds to select the next data line based on the output select signal;wherein the operating steps (a) and (b) are performed with respect toeach of the plural data lines connected to the driver via the selectorto complete current programming for the current load cells correspondingto one cycle.
 23. A semiconductor device driving method for driving asemiconductor device comprising: a plurality of data lines running inone direction on a substrate; a plurality of control lines running in adirection perpendicular to the data lines; a plurality of current loadcells each of which is set at the intersection of the respective datalines and control lines, and includes a current load and a current loaddriving circuit for driving the current load; and a selector having aninput terminal to which one current output from a driver forcurrent-driving the data lines is input, and a plurality of outputterminals connected to the plural data lines, respectively; wherein: theselector selects one of the plural data lines according to an outputselect signal input therein, and supplies the current output from thedriver to the selected data line; the plural data lines connected to theselector are connected to their corresponding current load cells,respectively; the current load driving circuit in each of the currentload cells includes: a first MOS transistor whose source is connected toa first power supply while whose drain is connected to one end of thecurrent load, the other end of the current load being connected to asecond power supply; a capacitance whose one end is connected to thegate of the first MOS transistor while whose the other end is connectedto the first power supply or another power supply; and a first switchwhose one end is connected to a contact node between the gate of thefirst MOS transistor and one end of the capacitance while whose theother end is connected to a corresponding data line via a second switch;there are control lines each transmitting a control signal correspondingto the first switch of the current load driving circuit in each of thecurrent load cells connected respectively to the data lines connected tothe selector; there is a common control line for transmitting a commoncontrol signal corresponding to the second switch of the current loaddriving circuit in each of the current load cells; the control signalbeing individual to each of the current load cells is supplied to thecontrol terminal of the first switch of the current load driving circuitin the current load cell; and the common control signal is supplied tothe control terminal of the second switch of the current load drivingcircuit in the current load cell; the semiconductor device drivingmethod, wherein one cycle is divided into a number of driving periodscorresponding to the plural current load cells connected respectively tothe plural data lines connected to the driver via the selector, and thesecond switch in the current load cell is on during one cycle accordingto the common control signal, comprising the steps of: (a) selecting onecorresponding data line from the plural data lines by the selector basedon the output select signal during each driving period corresponding toeach of the plural current load cells; (b) passing current correspondingto the current output supplied from the driver to the data line throughthe first MOS transistor in the current load cell by turning on thefirst switch in the current load cell with a control signal transmittedthrough one of the control lines for the current load cell correspondingto the data line selected by the selector; and (c) turning off the firstswitch with a control signal transmitted through the control line forthe current load cell corresponding to the data line selected at step(a) before or at the time the selector proceeds to select the next dataline based on the output select signal; wherein the operating steps (a)and (b) are performed with respect to each of the plural data linesconnected to the driver via the selector to complete current programmingfor the current load cells corresponding to one cycle.
 24. Thesemiconductor device driving method claimed in claim 22 for driving thesemiconductor device further comprising a second MOS transistor whosesource is connected to the first power supply and whose gate and drainare connected to each other; wherein the first switch is connectedbetween the gate of the second MOS transistor and the contact nodeconnecting the gate of the first MOS transistor with one end of thecapacitance; and the second switch is placed between the drain of thesecond MOS transistor and a corresponding data line.
 25. A semiconductordevice driving method for driving a semiconductor device comprising: aplurality of data lines running in one direction on a substrate; aplurality of control lines running in a direction perpendicular to thedata lines; a plurality of current load cells each of which is set atthe intersection of the respective data lines and control lines, andincludes a current load and a current load driving circuit for drivingthe current load; and a selector having an input terminal to which onecurrent output from a driver for current-driving the data lines isinput, and a plurality of output terminals connected to the plural datalines, respectively; wherein: the selector selects one of the pluraldata lines according to an output select signal input therein, andsupplies the current output from the driver to the selected data line;the plural data lines connected to the selector are connected to theircorresponding current load cells, respectively; the current load drivingcircuit in each of the current load cells includes: a first MOStransistor whose source is connected to a first power supply while whosedrain is connected to one end of the current load via a switch (referredto as “third switch”), the other end of the current load being connectedto a second power supply; a capacitance whose one end is connected tothe gate of the first MOS transistor while whose the other end isconnected to the first power supply or another power supply; and a firstswitch whose one end is connected to a contact node between the gate ofthe first MOS transistor and one end of the capacitance while whose theother end is connected to a corresponding data line directly or via asecond switch; there are control lines each transmitting a controlsignal corresponding to each of the current load cells connectedrespectively to the data lines connected to the selector; in each of theplural current load cells, the control terminal of the first switch ofthe current load driving circuit or the control terminals of both thefirst and second switches are supplied with the control signal throughthe control line corresponding to each of the current load cells; afourth switch is placed between a contact node connecting one end of thecurrent load with the third switch and the second power supply; andthere are a common control line connected to the control terminal of thethird switch and a common control line connected to the control terminalof the fourth switch for the current load driving circuit in each of thecurrent load cells connected respectively to the data lines connected tothe selector; the semiconductor device driving method, wherein one cycleis divided into a number of driving periods corresponding to the pluralcurrent load cells connected respectively to the plural data linesconnected to the driver via the selector, comprising the steps of: (a)selecting one corresponding data line from the plural data lines by theselector based on the output select signal during each driving periodcorresponding to each of the plural current load cells; (b) turning onthe first switch or the first and second switches in the current loadcell with one of control signals for the current load cell correspondingto the data line selected by the selector, and setting the third switchto the off state with a control signal transmitted through the commoncontrol line so as to set the terminal voltage of the capacitanceconnected to the gate of the first MOS transistor to a voltagecorresponding to the current output supplied from the driver to the dataline; (c) turning off the first switch or the first and second switchesin the current load cell with a control signal for the current load cellcorresponding to the data line selected at step (a) before or at thetime the selector proceeds to select the next data line based on theoutput select signal; and (d) after the operating steps (a) and (b) areperformed with respect to each of the plural data lines connected to thedriver via the selector to set a current for the first MOS transistor ofthe respective current load cells corresponding to one cycle, turning onthe third switch subsequently to the previous cycle so that the draincurrent of the first MOS transistor in the current load cell is suppliedto the current load cell.
 26. A semiconductor device driving method fordriving a semiconductor device comprising: a plurality of data linesrunning in one direction on a substrate; a plurality of control linesrunning in a direction perpendicular to the data lines; a plurality ofcurrent load cells each of which is set at the intersection of therespective data lines and control lines, and includes a current load anda current load driving circuit for driving the current load; and aselector having an input terminal to which one current output from adriver for current-driving the data lines is input, and a plurality ofoutput terminals connected to the plural data lines, respectively;wherein: the selector selects one of the plural data lines according toan output select signal input therein, and supplies the current outputfrom the driver to the selected data line; the plural data linesconnected to the selector are connected to their corresponding currentload cells, respectively; the current load driving circuit in each ofthe current load cells includes: a first MOS transistor whose source isconnected to a first power supply while whose drain is connected to oneend of the current load via a switch (referred to as “third switch”),the other end of the current load being connected to a second powersupply; a capacitance whose one end is connected to the gate of thefirst MOS transistor while whose the other end is connected to the firstpower supply or another power supply; and a first switch whose one endis connected to a contact node between the gate of the first MOStransistor and one end of the capacitance while whose the other end isconnected to a corresponding data line via a second switch; there arecontrol lines each transmitting a control signal corresponding to thefirst switch of the current load driving circuit in each of the currentload cells connected respectively to the data lines connected to theselector; there is a common control line corresponding to the secondswitch of the current load driving circuit in each of the current loadcells; the control terminal of the first switch of the current loaddriving circuit in the current load cell is supplied with the controlsignal through the control line corresponding to each of the currentload cells; the control terminal of the second switch of the currentload driving circuit in the current load cell is supplied with a controlsignal through the common control line; a fourth switch is placedbetween a contact node connecting one end of the current load with thethird switch and the second power supply; and there are a common controlline connected to the control terminal of the third switch and a commoncontrol line connected to the control terminal of the fourth switch forthe current load driving circuit in each of the current load cellsconnected respectively to the data lines connected to the selector; thesemiconductor device driving method, wherein one cycle is divided into anumber of driving periods corresponding to the plural current load cellsconnected respectively to the plural data lines connected to the drivervia the selector, and the second switch in the current load cell is onwhile the third switch is off during one cycle according to the controlsignal transmitted through the common control line, comprising the stepsof: (a) selecting one corresponding data line from the plural data linesby the selector based on the output select signal during each drivingperiod corresponding to each of the plural current load cells; (b)turning on the first switch in the current load cell with one of controlsignals for the current load cell corresponding to the data lineselected by the selector so as to set the terminal voltage of thecapacitance connected to the gate of the first MOS transistor to avoltage corresponding to the current output supplied from the driver tothe data line; (c) turning off the first switch with a control signalfor the current load cell corresponding to the data line selected atstep (a) before or at the time the selector proceeds to select the nextdata line based on the output select signal; and (d) after the operatingsteps (a) and (b) are performed with respect to each of the plural datalines connected to the driver via the selector to set a current for thefirst MOS transistor of the respective current load cells correspondingto one cycle, turning on the third switch subsequently to the previouscycle so that the drain current of the first MOS transistor in thecurrent load cell is supplied to the current load cell.
 27. Thesemiconductor device driving method claimed in claim 25, wherein, atoperating step (d), the period while the fourth switch is on is equal toor included in the period while the third switch is off.
 28. Thesemiconductor device driving method claimed in claim 22, wherein thecurrent load is formed of a light emitting element, and one cycle is onehorizontal period.
 29. A semiconductor device comprising: a plurality ofdata lines running in one direction; a plurality of control linesrunning in a direction perpendicular to the data lines; and a matrix ofcurrent load cells each of which is set at the intersection of therespective data lines and control lines; wherein each of the currentload cells includes: a current load; and a current load driving circuitfor driving the current load, having: a transistor connected in serieswith the current load between first and second power supplies; acapacitance connected between the control terminal of the transistor andthe first power supply; and at least one switch connected between thecontrol terminal of the transistor and a corresponding data line; andwherein there are control lines for controlling the switch at least asmany as data lines selectable by one current output of a current driverin one line of the semiconductor device; and one current output of thecurrent driver is connected to the plural data lines via a selector, andthe plural data lines connected to one current output of the currentdriver via the selector and at least one switch of each of the currentload cells corresponding to the respective data lines aredrive-controlled in a time division manner during one horizontal period.